Technology scaling has generally improved the speed in manufacturing ICs that embody a particular circuit design, and has further improved the efficient use of the “real estate” area of ICs. Technology scaling has also generally caused power behavior to become a substantive design objective for many classes of ICs and for systems/devices that include the ICs. Initially, power switching was the dominant power consideration in the design process. However, technology scaling has had an impact on the static (leakage) power consumption of circuits. Due to unabated silicon feature scaling, elevated leakage current has thus become an increasingly dominant power consideration in the recent and future designs of ICs. Indeed, there are predictions that leakage current will surpass power switching as the dominant design consideration in upcoming generations of scaled circuit designs.
To reduce the dynamic power (as opposed to static power) consumption, supply voltages have been scaled down as needed during operation of the circuit. To sustain performance, threshold voltages (Vt) have also been scaled down, but such scaling-down also may produce significant sub-threshold leakage current. Other variable factors, such as reverse junction bias, also may contribute to the leakage current.
Leakage current may be significant for devices that have low duty cycle modes (e.g., sleep modes), such as sensor network nodes and cellular telephones as examples. Leakage current may also be significant in “ultra-large” chips (e.g., systems-on-chip and network-on-chip architectures), where at any particular moment, a rather large percentage of gates may be in sleep mode because of temporarily lower workloads.
Device-level, circuit-level, and system-level techniques have been proposed to reduce leakage current in an IC, by controlling the input information or an input signal (sometimes referred to as an “input vector”) that is provided to the IC. Input vector control (IVC) may be an effective technique to minimize the leakage current because in a circuit's sleep state, the leakage current generally depends on the combination of values (e.g., binary values) of the input vector. However, such conventional IVC techniques may not efficiently determine the value(s) of the input vector that will result in the reduction or minimization of leakage current for a large number of ICs.